Oscillation devices have been widely used for wireless devices for analog communications (transmitters and/or receivers), wireless devices for data communications (telemetry), or the like. Recently, PLL frequency synthesizers employing a phase locked loop (PLL) are widely used as oscillation devices in such wireless devices. Since, in the PLL frequency synthesizers, the oscillation frequency can be varied in a wide range with high frequency stability, the PLL frequency synthesizers are being widely used for household and industrial applications without being limited to the wireless devices.
FIG. 6 shows a conventional PLL frequency synthesizer 100. The PLL frequency synthesizer 100 includes a reference oscillator 101 made of, for example, a crystal oscillator; a 1/M frequency divider 102 made of a 1/M frequency dividing counter; a phase comparator 103 made of an exclusive-OR circuit; a loop filter 104 made of a lag filter and a lead filter; a voltage-controlled oscillator (VCO) 105; and a 1/N frequency divider 106 made of a programmable frequency dividing counter whose frequency dividing ratio N is variable.
The PLL frequency synthesizer 100 is configured by combining the aforementioned components as will be described hereinafter. An output end of the reference oscillator 101 is connected with an input end of the 1/M frequency divider 102; an output end of the 1/M frequency divider 102 is connected with one input end of the phase comparator 103; the other input end of the phase comparator 103 is connected with an output end of the 1/N frequency divider 106; an output end of the phase comparator 103 is connected with an input end of the loop filter 104; an output end of the loop filter 104 is connected with an input end of the voltage-controlled oscillator 105; and an output end of the voltage-controlled oscillator 105 is connected with an input end of the 1/N frequency divider 106.
With such configuration, the PLL frequency synthesizer serves as a feedback control system and operates as will be described later, thereby obtaining an output oscillation signal Sfo having a frequency of an integral multiple of that of a frequency dividing reference signal Sfm, wherein the integral multiple is equal to the frequency dividing ratio N. Herein, the frequency dividing reference signal Sfm has a frequency of 1/M times that of a reference oscillation signal Sfs.
First of all, the reference oscillation signal Sfs outputted from the reference oscillator 101 is frequency-converted into the frequency dividing reference signal Sfm of a lower oscillation frequency, wherein the oscillation frequency of the reference oscillation signal Sfs is divided by 1/M by the 1/M frequency dividing counter. By dividing the frequency of the reference oscillation signal Sfs by 1/M, even when a crystal oscillator, for example, is used as the reference oscillator 101, various frequencies of the output oscillation signal Sfo can be obtained in a discrete manner at a fine step while achieving a reduction in cost and size.
The phase comparator 103 compares a phase of the frequency dividing reference signal Sfm with that of the output frequency dividing signal Sfn. The phases are compared by measuring a time difference between a rising edge of a binarized frequency dividing reference signal Sfm and that of a binarized output oscillation signal Sfo, thereby outputting a phase error signal Spe corresponding to the time difference therebetween. Moreover, the loop filter 104 performs a phase compensation on the phase error signal Spe to output a phase compensation error signal Scpe. By performing the phase compensation, the feedback control system secures a gain margin and a phase margin sufficiently large enough to allow it to optimize its performance. Furthermore, in the voltage-controlled oscillator 105, output oscillation signal Sfo is changed in accordance with the phase compensation error signal Scpe to thereby allow the feedback control system to be operated such that the phase error signal Spe becomes close to zero.
As a result of such operation of the feedback control system, a frequency of the frequency dividing reference signal Sfm becomes perfectly identical to that of the output frequency dividing signal Sfn. Further, a frequency of the output oscillation signal Sfo is identified by multiplying the frequency dividing reference signal Sfm by the frequency dividing ratio N of the 1/N frequency dividing counter.
The aforementioned PLL frequency synthesizer can serve as a variable frequency oscillation device for oscillating widely ranging frequencies of signals by using the feedback control system. Further, it is possible to obtain an oscillation signal having a frequency accuracy approximately equal to that of the reference oscillation signal Sfs, e.g., that of the oscillation signal of the crystal oscillator. Moreover, even when the PLL frequency synthesizer serves not as the variable frequency oscillation device but as a fixed frequency oscillation device, since the setting a frequency thereof is so easy, a desired oscillation frequency can be easily obtained without requiring an additional crystal oscillator for every desired frequency. Moreover, by making the device more general-purposed, the costs of the oscillation device can be reduced.
However, the PLL frequency synthesizer consumes a large amount of power because of a large number of circuit devices. Especially, as an oscillation frequency increases, an increased current consumption in the reference oscillator causes a great loss, i.e., a switching loss generated at every clock period in digital circuits such as a frequency dividing counter and a phase comparator. Since the current consumption is large, it is difficult to operate for a long time wireless devices driven by a battery or a solar battery, e.g., a wireless telemetry device installed deep in a mountain, a wireless radio control device for wirelessly controlling a model plane or the like. Similar drawbacks are also found in case the PLL frequency synthesizer is made of an integrated circuit (IC).